The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
May. 31, 2022
Pass & Seymour, Inc., Syracuse, NY (US);
Brian Mueller, Cortland, NY (US);
Joshua P. Haines, Marcellus, NY (US);
David A. Finlay, Sr., Marietta, NY (US);
Gerald R. Savicki, Jr., Canastota, NY (US);
Pass & Seymour, Inc., Syracuse, NY (US);
Abstract
An electrical wiring device including a housing assembly including a plurality of terminals at least partially disposed therein, the plurality of terminals including a HOT/LOAD terminal, a NEUTRAL terminal, a first traveler terminal, and a second traveler terminal, wherein, when in use, at least one of the terminals is connected to line hot; a first series FET and a second series FET disposed in series between the HOT/LOAD terminal and one of the first traveler terminal or the second traveler terminal; at least one of a first sensor producing a first sensor output according to current flow or a voltage at the one of the first traveler terminal or the second traveler terminal and a second sensor producing a second sensor output according to current flow through the NEUTRAL terminal or according to a voltage between the first series FET and second series FET; and a controller configured to determine to which of the plurality of terminals line hot is connected based, at least, on the first sensor output or the second sensor output and to provide, during operation, at least one of a first control signal to the first series FET and a second control signal to the second series FET according to a user adjustable load setting.