The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Jun. 03, 2021
Applicant:

Nichia Corporation, Anan, JP;

Inventors:

Shun Kitahama, Tokushima, JP;

Yoshiki Inoue, Anan, JP;

Kazuhiro Nagamine, Komatsushima, JP;

Junya Narita, Yoshinogawa, JP;

Assignee:

NICHIA CORPORATION, Anan, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/44 (2010.01); H01L 33/38 (2010.01); H01L 33/14 (2010.01); H01L 33/32 (2010.01); H01L 33/22 (2010.01); H01L 21/268 (2006.01);
U.S. Cl.
CPC ...
H01L 33/0095 (2013.01); H01L 33/007 (2013.01); H01L 33/0075 (2013.01); H01L 33/145 (2013.01); H01L 33/32 (2013.01); H01L 33/382 (2013.01); H01L 33/44 (2013.01); H01L 21/268 (2013.01); H01L 33/22 (2013.01); H01L 2933/0025 (2013.01);
Abstract

A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer located on the substrate, and a p-side nitride semiconductor layer located on the n-side nitride semiconductor layer, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; a first protective layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer; and a current diffusion layer located on and in direct contact with an upper face of the p-side nitride semiconductor layer in a region corresponding to the area inside of the peripheral portion. The current diffusion layer does not overlap the first protective layer in a top view.


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