The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 19, 2022
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Seong-Hyun Kim, Suwon, KR;

Jung-Won Seo, Suwon, KR;

An-Na Choi, Seoul, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 63/00 (2023.01); H01L 21/764 (2006.01); H10B 43/30 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5329 (2013.01); H01L 21/7682 (2013.01); H01L 23/5226 (2013.01); H10B 63/84 (2023.02); H01L 21/764 (2013.01); H10B 43/30 (2023.02); H10B 63/24 (2023.02); H10N 70/231 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02);
Abstract

An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.


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