The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Feb. 25, 2021
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Andrew Clarke, Santa Barbara, CA (US);

John J. Drab, Arroyo Grande, CA (US);

Faye Walker, Lompoc, CA (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76883 (2013.01); H01L 21/76802 (2013.01); H01L 21/76886 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53233 (2013.01);
Abstract

A CuSn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the CuSn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a CuSn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed CuSn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.


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