The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Jul. 09, 2021
Applicant:
Imec Vzw, Leuven, BE;
Inventors:
Boon Teik Chan, Wilsele, BE;
Pierre Morin, Woluwe-Saint-Pierre, BE;
Antony Premkumar Peter, Heverlee, BE;
Assignee:
IMEC VZW, Leuven, BE;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); H01L 21/0228 (2013.01); H01L 21/02274 (2013.01); H01L 21/02282 (2013.01); H01L 21/3212 (2013.01); H01L 21/823431 (2013.01); H01L 29/6681 (2013.01);
Abstract
A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.