The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Aug. 16, 2022
Texas Instruments Incorporated, Dallas, TX (US);
Sriramakrishnan Govindarajan, Bengaluru, IN;
Denis Roland Beaudoin, Rowlett, TX (US);
Gregory Raymond Shurtz, Houston, TX (US);
Santhanakrishnan Badri Narayanan, Bengaluru, IN;
Mark Adrian Bryans, Dallas, TX (US);
Mihir Narendra Mody, Bengaluru, IN;
Jason A. T. Jones, Richmond, TX (US);
Jayant Thakur, Bengaluru, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.