The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Jun. 08, 2020
Applicant:

Xerox Corporation, Norwalk, CT (US);

Inventor:

Daniel Davies, Palo Alto, CA (US);

Assignee:

XEROX CORPORATION, Norwalk, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/4265 (2013.01); G06F 15/17362 (2013.01);
Abstract

A computing system framework and method for configuration thereof are provided. A plurality of processing modules are accessed. Each processing module includes a plurality of processing nodes and each processing node is associated with an intra-module port and an inter-module port. A plurality of intra-module networks are formed. Each intra-module network includes connections between at least a portion of the processing nodes in one of the processing modules via the associated intra-module ports. An enclosed shape of the processing modules is formed by connecting at one inter-module port on each processing module to one inter-module port on an adjacent processing modules. A cable is linked between one of the inter-module ports of one processing module of the enclosed shape to an inter-module port of another processing module of a different group of interconnected processing modules.


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