The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Sep. 13, 2022
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventors:
Assignee:
Kioxia Corporation, Tokyo, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H01L 23/562 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01);
Abstract
According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.