Address translation cache with use of page size information to select an invalidation lookup mode, or use of leaf-and-intermediate exclusive range-specifying invalidation request, or use of invalidation request specifying single address and page size information

Abstract

An apparatus has an address translation cache () having a number of cache entries () for storing address translation data which depends on one or more page table entries of page tables. Control circuitry () is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry () selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.