The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Nov. 17, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Arvind Kaushik, Noida, IN;

Aarul Jain, New Delhi, IN;

Nishant Jain, Noida, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1016 (2013.01); G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 2201/805 (2013.01);
Abstract

An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.


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