The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Apr. 28, 2022
Shenzhen Pango Microsystems Co., Ltd, Shenzhen, CN;
Lei Tian, Shenzhen, CN;
Yinghao Liao, Shenzhen, CN;
SHENZHEN PANGO MICROSYSTEMS CO., LTD, Shenzhen, CN;
Abstract
A power management system and method for an SRAM circuit and an FPGA chip are provided. The power management system includes a power management, a power management controller and an oscillator. The power management circuit include a power-on reset circuit used to determine whether powering-on of a core voltage and an analog input-output voltage of power supply voltages of the power management circuit is completed. The power management controller and the oscillator are used to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed, and further used to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on. Powering-on sequences of various internal power supplies of the FPGA chip are clear, and power consumption of the FPGA chip can be reduced.