The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Feb. 13, 2023
Applicant:

Sharp Kabushiki Kaisha, Osaka, JP;

Inventor:

Takahiro Mori, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1339 (2006.01); G02F 1/1345 (2006.01); G11C 19/28 (2006.01); G02F 1/1335 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1339 (2013.01); G02F 1/1345 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/133512 (2013.01); G02F 1/136213 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G11C 19/287 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0286 (2013.01);
Abstract

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.


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