The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Sep. 16, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Fumitaka Arai, Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/14 (2006.01); H10B 43/20 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); H10B 41/20 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/20 (2023.02); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H10B 41/20 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02);
Abstract

According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch.


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