The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Apr. 29, 2022
Applicant:

Coherent Logix, Incorporated, Austin, TX (US);

Inventors:

Michael W. Bruns, Portland, OR (US);

Martin A. Hunt, Austin, TX (US);

Manjunath H. Siddaiah, Cedar Park, TX (US);

John C. Sievers, Lynnfield, MA (US);

Assignee:

Coherent Logix, Incorporated, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 19/43 (2014.01); H04N 19/436 (2014.01); G06F 9/38 (2018.01); H04N 19/176 (2014.01); H04N 19/146 (2014.01); H04N 19/107 (2014.01); H04N 19/147 (2014.01);
U.S. Cl.
CPC ...
H04N 19/436 (2014.11); G06F 9/3877 (2013.01); H04N 19/107 (2014.11); H04N 19/146 (2014.11); H04N 19/147 (2014.11); H04N 19/176 (2014.11);
Abstract

Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.


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