The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

May. 15, 2020
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

June Hwan Kim, Daejeon, KR;

Tae Young Kim, Seongnam-si, KR;

Jong Woo Park, Seongnam-si, KR;

Young Tae Choi, Cheonan-si, KR;

Hyun Cheol Hwang, Seoul, KR;

Ki Ju Im, Suwon-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10K 59/121 (2023.01);
U.S. Cl.
CPC ...
H01L 27/1237 (2013.01); H01L 27/1218 (2013.01); H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02);
Abstract

A display device is provided. The display device comprises a substrate, a first buffer layer on the substrate, a first semiconductor layer on the first buffer layer and including a first active layer, a first gate insulating layer on the first semiconductor layer and the first buffer layer and covering the first active layer, a first conductive layer on the first gate insulating layer and including a first gate electrode, a second conductive layer on the first conductive layer and including a first source/drain electrode, a first interlayer insulating layer on the first conductive layer, a second semiconductor layer on the first interlayer insulating layer and including a second active layer, a second gate insulating layer on the second semiconductor layer and covering the second active layer, and a third conductive layer on the second gate insulating layer and including a second gate electrode and a second source/drain electrode, wherein the first gate insulating layer and the second gate insulating layer include different insulating materials.


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