The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Sep. 02, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Mengyue Fan, Beijing, CN;

Wenbo Chen, Beijing, CN;

Zhongliu Yang, Beijing, CN;

Bing Zhang, Beijing, CN;

Chenyu Chen, Beijing, CN;

Shuang Zhao, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G11C 19/287 (2013.01); H10K 59/131 (2023.02); H10K 71/00 (2023.02); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); H10K 59/1201 (2023.02);
Abstract

A display substrate, including: a display region and a peripheral region located on the periphery of the display region. A scan driver circuit is disposed in the peripheral region. A plurality of sub-pixels, and a plurality of first signal lines that are connected to the scan driver circuit and extend in a first direction, are disposed in the display region. The display region includes: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer that are sequentially disposed on the substrate. The third conductive layer comprises: a plurality of first signal lines, and first electrodes and second electrodes of a plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with first via holes.


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