The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Jul. 29, 2022
Applicant:

Arista Networks, Inc., Santa Clara, CA (US);

Inventors:

Chen Jia Jang, Burnaby, CA;

Suhas Raghunath Joshi, San Jose, CA (US);

Ganesan Venkataraman, Sunnyvale, CA (US);

Assignee:

Arista Networks, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/065 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01);
Abstract

A logical table is configured with a first set of memory banks, where each logical row in the logical table comprises a corresponding memory row from each of the memory banks. Lookup instructions to access a logical row includes a bank set that lists the memory banks associated with that logical row. In response to a range of memory rows of one of the memory banks being reallocated to another logical table, a new memory bank is identified to store the data in the reallocated memory rows. Logical rows associated with the reallocated memory rows are mapped to the new memory bank. Bank sets in the lookup instructions that refer to the remapped logical rows are updated to list the new memory bank in place of the 'old' memory bank.


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