The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Dec. 01, 2020
Applicant:

Fujitsu Limited, Kawasaki, JP;

Inventors:

Kazuto Nishimura, Yokohama, JP;

Nobuhiro Rikitake, Machida, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04W 72/12 (2023.01); H04W 72/1263 (2023.01); H04L 5/14 (2006.01);
U.S. Cl.
CPC ...
H04W 72/1263 (2013.01); H04L 5/14 (2013.01);
Abstract

A packet processing apparatus includes a memory, a processor, a first gate, and a second gate. The memory stores a plurality of allocation patterns for allocating an upstream or downstream of a link direction for each subframe within a predetermined period. The processor obtains a periodicity pattern of a high-priority packet for each of time slots within the subframe. The first gate opens and closes, for each of the time slots within the subframe, output of the high-priority packet. The second gate opens and closes, for each of the time slots within the subframe, output of a low-priority packet. The processor sets gate states of the first gate and the second gate for a predetermined time slot within the subframe in the same link direction as the periodicity pattern to a priority state in which the high-priority packet is preferentially output according to the periodicity pattern.


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