The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Apr. 28, 2023
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Lei Zou, Oslo, NO;

Sindre Mikkelsen, Ski, NO;

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/767 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01);
U.S. Cl.
CPC ...
H04N 25/709 (2023.01); H04N 25/767 (2023.01); H04N 25/77 (2023.01);
Abstract

An imaging system includes a pixel array with pixel circuits, each including a photodiode, a floating diffusion, a source follower transistor, and a row select transistor. The imaging system further includes rolling clamp (RC) drivers, each coupled to a gate terminal of a row select transistor of one of the pixel circuits and each including first and second PMOS transistors coupled between a clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits, and first, second, and third NMOS transistors coupled between the clamp voltage and the gate terminal of the row select transistor of the one of the pixel circuits. The PMOS transistors and the NMOS transistors are coupled in parallel. The PMOS transistors are configured to provide an upper clamp voltage range, and the NMOS transistors are configured to provide a lower clamp voltage range.


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