The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jun. 10, 2022
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Vladimir Vitalievich Gritsenko, Moscow, RU;

Vladislav Nikolaevich Obolentsev, Moscow, RU;

Dmitrii Yurievich Bukhan, Moscow, RU;

Aleksei Eduardovich Maevskii, Moscow, RU;

Hongchen Yu, Beijing, CN;

Kun Gu, Beijing, CN;

Jie Chen, Wuhan, CN;

Shiyao Xiao, Chengdu, CN;

Man Zhao, Chengdu, CN;

Jun Chen, Chengdu, CN;

Yunlong Li, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0041 (2013.01); H04L 1/0045 (2013.01); H04L 1/0071 (2013.01);
Abstract

The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.


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