The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jan. 12, 2022
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:
Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/099 (2006.01); G11C 7/10 (2006.01); G11C 7/16 (2006.01); H03L 7/081 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0991 (2013.01); G11C 7/1036 (2013.01); G11C 7/16 (2013.01); H03L 7/081 (2013.01); H03L 7/085 (2013.01);
Abstract

A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter () comprising: an oscillator () configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (-), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage () configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (-).


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