The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jan. 03, 2023
Applicant:

Silicon Motion, Inc., Hsinchu County, TW;

Inventors:

Tien-Hsing Yao, Taipei, TW;

Chun-Cheng Lee, Yilan County, TW;

Sheng-I Hsu, Hsinchu County, TW;

Assignee:

Silicon Motion, Inc., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/02 (2006.01); H03K 21/08 (2006.01); H03K 21/10 (2006.01); G06F 1/3234 (2019.01); H03K 5/00 (2006.01); H03K 21/40 (2006.01);
U.S. Cl.
CPC ...
H03K 21/026 (2013.01); G06F 1/3275 (2013.01); H03K 5/00006 (2013.01); H03K 21/10 (2013.01); H03K 21/406 (2013.01);
Abstract

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.


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