The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jan. 19, 2021
Applicant:

Rosemount Inc., Shakopee, MN (US);

Inventors:

Scott T. Hofmeister, Chaska, MN (US);

Cody J. Skow, Shakopee, MN (US);

Allen J. Kempke, Minneapolis, MN (US);

Nicholas A. Wienhold, Waconia, MN (US);

Theodore H. Schnaare, Carver, MN (US);

Assignee:

ROSEMOUNT INC., Shakopee, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01C 7/12 (2006.01); H02H 1/00 (2006.01); H02H 1/04 (2006.01); H02H 3/22 (2006.01); H02H 9/06 (2006.01); H02H 9/00 (2006.01); H04W 88/16 (2009.01); H04B 10/80 (2013.01); H04L 12/10 (2006.01); H04W 84/18 (2009.01);
U.S. Cl.
CPC ...
H02H 9/008 (2013.01); H04B 10/802 (2013.01); H04L 12/10 (2013.01); H04W 88/16 (2013.01); H04W 84/18 (2013.01);
Abstract

A wireless sensor network gateway includes safe side circuitry, hazardous side circuitry and isolation circuitry, which are supported by a housing. The safe side circuitry includes a safe side power circuit, and a safe side data input/output (I/O) circuit. The hazardous side circuitry includes a hazardous side power circuit, and a hazardous side data I/O circuit. The isolation circuitry divides the safe side circuitry from the hazardous side circuitry. The isolation circuitry includes a power isolation circuit that couples the safe side power circuit to the hazardous side power circuit and forms an intrinsic safety barrier between the safe side power circuit and the hazardous side power circuit, and a data isolation circuit that couples the safe side data I/O circuit to the hazardous side data I/O circuit and forms an intrinsic safety barrier between the safe side data I/O circuit and the hazardous side data I/O circuit.


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