The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2023
Filed:
Apr. 22, 2022
Method of manufacturing mosfet having a semiconductor base substrate with a super junction structure
Shindengen Electric Manufacturing Co., Ltd., Tokyo, JP;
Daisuke Arai, Saitama, JP;
Mizue Kitada, Saitama, JP;
Takeshi Asada, Saitama, JP;
Noriaki Suzuki, Saitama, JP;
Koichi Murakami, Saitama, JP;
SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., Tokyo, JP;
Abstract
A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.