The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 18, 2020
Applicant:

D-wave Systems Inc., Burnaby, CA;

Inventors:

Loren J. Swenson, San Jose, CA (US);

George E. G. Sterling, Vancouver, CA;

Christopher B. Rich, Vancouver, CA;

Assignee:

D-WAVE SYSTEMS INC., Burnaby, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 60/12 (2023.01); G11C 11/44 (2006.01); H03K 3/38 (2006.01); H03K 17/92 (2006.01); G11C 8/00 (2006.01); G06N 10/40 (2022.01); G11C 8/10 (2006.01); H10N 60/80 (2023.01); H10N 69/00 (2023.01);
U.S. Cl.
CPC ...
H10N 60/12 (2023.02); G06N 10/40 (2022.01); G11C 8/00 (2013.01); G11C 8/10 (2013.01); G11C 11/44 (2013.01); H03K 3/38 (2013.01); H03K 17/92 (2013.01); H10N 60/805 (2023.02); H10N 69/00 (2023.02);
Abstract

Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.


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