The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Dec. 04, 2020
Applicant:

United Microelectronics Center Co., Ltd, Chongqing, CN;

Inventors:

Miao Wang, Chongqing, CN;

Weimong Tsang, Chongqing, CN;

Wenlong Jiao, Chongqing, CN;

Haopeng Wang, Chongqing, CN;

Ruifeng Yang, Chongqing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 39/00 (2023.01); G01L 1/16 (2006.01); H01L 21/78 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H10N 39/00 (2023.02); G01L 1/16 (2013.01); H01L 21/78 (2013.01); H01L 25/0655 (2013.01);
Abstract

The present disclosure provides a flexible integrated array sensor and manufacturing methods thereof. The array sensor includes a silicon wafer, a readout circuit layer, a sensing array layer, and a polymer substrate layer disposed on the silicon wafer. The manufacturing method includes: preparing a silicon wafer; fabricating a plurality of function arrays, each including m*n function units, on a surface of the silicon wafer; etching one or more deep grooves on the surface of the silicon wafer between the arrays; fabricating a thinning support; and thinning a bottom surface of the silicon wafer to a target thickness so that the arrays are separated from each other. The etching depth for etching the one or more deep grooves is equal to or greater than the thickness of the silicon wafer after thinning.


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