The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2023
Filed:
Nov. 04, 2019
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;
Huaxiang Yin, Beijing, CN;
Zhaozhao Hou, Beijing, CN;
Tianchun Ye, Beijing, CN;
Chaolei Li, Beijing, CN;
Abstract
Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.