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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11839084 B1

PDFFull Text
Date of Patent:
Dec. 05, 2023

Filed:

May. 26, 2022

Three-dimensional semiconductor memory devices having a vertical semiconductor pattern

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Euntaek Jung, Seongnam-si, KR;

JoongShik Shin, Yongin-si, KR;

JiHye Yun, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Patricia D Valenzuela

Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/285 (2006.01); H01L 21/28 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H01L 23/522 (2006.01); H10B 41/50 (2023.01); H10B 43/50 (2023.01); H10B 69/00 (2023.01); H01L 29/66 (2006.01); H10B 43/30 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/28525 (2013.01); H01L 21/76868 (2013.01); H01L 23/528 (2013.01); H01L 23/53271 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/66833 (2013.01); H10B 41/50 (2023.02); H10B 43/30 (2023.02); H10B 43/50 (2023.02); H10B 69/00 (2023.02);
Abstract

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

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