The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 04, 2021
Applicant:

Fermi Research Alliance, Llc, Batavia, IL (US);

Inventors:

Farah Fahim, Glen Ellyn, IL (US);

Tom Zimmerman, St. Charles, IL (US);

Grzegorz Deptuch, Forest Park, IL (US);

Assignee:

Fermi Research Alliance, LLC, Batavia, IL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/75 (2023.01); H03M 1/46 (2006.01); H03K 5/24 (2006.01); H04N 25/709 (2023.01); H04N 25/766 (2023.01);
U.S. Cl.
CPC ...
H04N 25/75 (2023.01); H03K 5/2472 (2013.01); H03M 1/462 (2013.01); H03M 1/466 (2013.01); H04N 25/709 (2023.01); H04N 25/766 (2023.01);
Abstract

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.


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