The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

May. 07, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Taeyoung Song, Hwaseong-si, KR;

Sung In Kim, Hwaseong-si, KR;

Kwansik Cho, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14614 (2013.01); H01L 24/08 (2013.01); H01L 27/1462 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14645 (2013.01); H01L 27/14689 (2013.01); H01L 2224/08145 (2013.01);
Abstract

An image sensor may include a substrate having first and second surfaces opposite to each other and including unit pixel regions and impurity regions near the first surface, a device isolation pattern provided on the first surface to define the impurity regions, and an interconnection layer including an insulating layer covering the first surface of the substrate, interconnection lines on the insulating layer, and a penetration structure penetrating the insulating layer. The penetration structure may include a first pattern connected to one of the impurity regions and in contact with at least a portion of the device isolation pattern, a second pattern provided on the first pattern and in contact with the interconnection lines, and a third pattern provided between the first and second patterns. A top surface of the first pattern may be higher than that of the device isolation pattern.


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