The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2023
Filed:
Feb. 22, 2022
Realtek Semiconductor Corporation, Hsinchu, TW;
Shih-Hsiung Huang, Hsinchu, TW;
REALTEK SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Abstract
A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor. The outer wells and the outer second conductors jointly function as a dummy capacitor structure.