The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 31, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hema Ramamurthy, Austin, TX (US);

Michael Lee, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 15/04 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 15/04 (2013.01); G11C 7/12 (2013.01); G11C 11/419 (2013.01);
Abstract

A compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. The CAM devices includes a transmission gate, having a positive field effect transistor ('PFET') and a negative field effect transistor ('NFET'), configured to compare a compare data input with storage node data having a first logic state. The CAM devices includes a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input, and the storage node data of a storage cell is used to control the passgate based on the storage node data. The CAM devices includes a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state.


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