The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Jan. 19, 2021
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Vinod Parackal Saby, Bangalore, IN;

Krishnaprasad Koladi, Bengaluru, IN;

Gobind Vijayakumar, Trichy, IN;

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 11/30 (2006.01); G06F 11/07 (2006.01); G06F 12/14 (2006.01); G06F 11/14 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 11/0772 (2013.01); G06F 11/1446 (2013.01); G06F 11/3037 (2013.01); G06F 12/02 (2013.01); G06F 12/1416 (2013.01); G06F 2009/45583 (2013.01);
Abstract

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive a request for a secure memory region with fault resiliency from first processor instructions being executed at a first processor privilege level; allocate a first enclave, in which the first enclave protects at least one of second processor instructions and data from being read by and from being altered by third processor instructions executing at a second processor privilege level; allocate a second enclave, in which the second enclave protects the at least one of the second processor instructions and the data from being read by and from being altered by the second processor instructions; store the at least one of the second processor instructions and the data in the first enclave; and mirror the at least one of the second processor instructions and the data in the second enclave.


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