The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Sep. 15, 2020
Applicant:

Alibaba Group Holding Limited, Grand Cafyman, KY;

Inventors:

Ziyi Hao, Hangzhou, CN;

Chen Chen, Shanghai, CN;

Xiaoyan Xiang, Shanghai, CN;

Feng Zhu, Hangzhou, CN;

Assignee:

Alibaba Group Holding Limited, Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/0895 (2016.01); G06F 12/0882 (2016.01); G06F 9/30 (2018.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/30047 (2013.01); G06F 9/30101 (2013.01); G06F 12/0882 (2013.01); G06F 12/0895 (2013.01); G06F 12/1063 (2013.01); G06F 2212/1021 (2013.01);
Abstract

A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes: at least one translation look-aside buffer, configured to store a plurality of cache entries, where the plurality of cache entries include a plurality of level 1 cache entries and a plurality of level 2 cache entries; and an address translation unit, coupled to the at least one translation look-aside buffer, and adapted to translate, based on one of the plurality of level 1 cache entries, a virtual address specified by a translation request into a corresponding translated address, or when the translation request does not hit any one of the plurality of level 1 cache entries, translate, based on one of the plurality of level 2 cache entries, a virtual address specified by the translation request into a corresponding translated address. In embodiments of the present disclosure, a hierarchical search is performed among the plurality of cache entries based on the virtual address specified by the translation request. Therefore, time required by searching for a cache entry in an address translation process is reduced, efficiency, frequency, and performance of a processor are improved, and power consumption is reduced.


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