The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Jul. 15, 2021
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventor:

Ching Wei Chang, Cedar Park, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 11/07 (2006.01); H04W 52/02 (2009.01); G06F 1/28 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3058 (2013.01); G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 11/0724 (2013.01); G06F 11/0751 (2013.01);
Abstract

An information handling system includes a failsafe circuit connected to a first power control interconnect conductor, to a second power control interconnect conductor, and to a processor status interconnect conductor. A processor may provide a first level indicating an operational status of the processor to the processor status interconnect conductor when the processor is operational, and provide a second level indicating a non-operational status of the processor to the processor status interconnect conductor when the processor is non-operational. The failsafe circuit may assure, upon provision of the second level to the processor status interconnect conductor, that the first power control interconnect conductor will be in a first failsafe state and the second power control interconnect conductor will be in a second failsafe state.


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