The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Aug. 09, 2021
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ashish Kumar Nayak, San Jose, CA (US);

Hugh Thomas Mair, San Jose, CA (US);

Anshul Varma, San Jose, CA (US);

Anand Rajagopalan, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); G01R 31/3193 (2006.01); H03K 5/134 (2014.01); G01R 31/317 (2006.01); G01R 31/30 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/3016 (2013.01); G01R 31/31937 (2013.01); H03K 3/0315 (2013.01); H03K 5/134 (2014.07);
Abstract

Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.


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