The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Nov. 03, 2020
Applicant:

Envistacom, Llc, Atlanta, GA (US);

Inventors:

Michael Beeler, Jefferson, MD (US);

Michael Geist, Huntersville, NC (US);

Cris Mamaril, Mesa, AZ (US);

Jason Duchez, Urbana, MD (US);

Jakob Harmon, Charlottesville, VA (US);

Richard Davis, Bel Air, MD (US);

Assignee:

APOTHYM TECHNOLOGIES GROUP, LLC, Peachtree Corners, GA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); H04L 25/03 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0045 (2013.01); H03M 13/11 (2013.01); H04L 25/03057 (2013.01);
Abstract

A method to provide flexibility on the configuration and operation of the modulator, demodulator, and modem, where purpose-built (legacy) devices are not traditionally capable of exposing a level of control and flexibly for a user or an autonomous program for optimizing performance. Providing user or programmatic control of algorithms is traditionally not possible for purpose-built modems. Parameters such as the number of decoder iterations that are performed on Forward Error Correction (FEC), Interference Mitigation algorithm, or dynamic adjustment loop bandwidth to combat phase noise can be adjusted autonomously to optimize receiver performance. The all software modem, supported by a High-Performance Computing (HPC) architecture, removes the limitation due to the flexibility of programming resources and available performance. Unlike most purpose-built hardware, the HPC allows processing resources to dynamically be reallocated, so that as additional performance is desired, the resources may be increased and decreased as required.


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