The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Oct. 14, 2022
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Kushal Das, Marsden Park, AU;

Alireza Moini, Beecroft, AU;

David J. Reilly, Sydney, AU;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/195 (2006.01); H02M 1/08 (2006.01); G06N 10/00 (2022.01); G06F 9/448 (2018.01); G06F 1/03 (2006.01); G06F 9/30 (2018.01); G11C 11/44 (2006.01); H02M 3/07 (2006.01); H10B 63/00 (2023.01); H04L 45/00 (2022.01); H04L 1/24 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1958 (2013.01); G06F 1/0321 (2013.01); G06F 9/30098 (2013.01); G06F 9/4498 (2018.02); G06N 10/00 (2019.01); G11C 11/44 (2013.01); H02M 1/08 (2013.01); H02M 3/07 (2013.01); H03K 19/195 (2013.01); H04L 1/24 (2013.01); H04L 7/033 (2013.01); H04L 45/40 (2013.01); H10B 63/30 (2023.02);
Abstract

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.


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