The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Sep. 17, 2021
Applicant:

Paragraf Limited, Somersham, GB;

Inventors:

Thomas James Badcock, Somersham, GB;

Robert Wallis, Somersham, GB;

Ivor Guiney, Somersham, GB;

Simon Thomas, Somersham, GB;

Assignee:

Paragraf Limited, Somersham, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/04 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66045 (2013.01); H01L 21/042 (2013.01); H01L 29/1606 (2013.01); H01L 29/7606 (2013.01); H01L 29/7839 (2013.01);
Abstract

The present invention provides a method of manufacturing a graphene transistor, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating regionand an adjacent semiconducting region; (b) forming a graphene layer structureon the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric materialon a portion of the graphene layer structure which is itself disposed on the semiconducting region; and (d) providing: a source contacton a portion of the graphene layer structure which is itself disposed on the insulating region; a gate contacton the layer of dielectric materialand above a portion of the graphene layer structure which is itself disposed on the semiconducting region; and a drain contacton the semiconducting regionof the substrate surface.


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