The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Feb. 08, 2022
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Namhoon Kim, San Jose, CA (US);

Woon-Seong Kwon, Santa Clara, CA (US);

Houle Gan, Santa Clara, CA (US);

Yujeong Shim, Cupertino, CA (US);

Mikhail Popovich, Danville, CA (US);

Teckgyu Kang, Saratoga, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01);
Abstract

The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.


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