The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Nov. 04, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Saurabh Nilkanth Athavale, Milpitas, CA (US);

Shrikar Bhagath, San Jose, CA (US);

Pradeep Rai, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 24/48 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.


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