The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Jul. 24, 2020
Applicants:

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Shan Zhang, Beijing, CN;

Lianjie Qu, Beijing, CN;

Yonglian Qi, Beijing, CN;

Hebin Zhao, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/765 (2006.01); H01L 21/762 (2006.01); H01L 21/683 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G06V 40/13 (2022.01);
U.S. Cl.
CPC ...
H01L 21/76254 (2013.01); H01L 21/6835 (2013.01); H01L 27/127 (2013.01); H01L 29/66772 (2013.01); H01L 29/78654 (2013.01); G06V 40/1318 (2022.01); H01L 2221/68368 (2013.01);
Abstract

A method of manufacturing thin film transistor(s) includes: providing a monocrystalline silicon wafer, the monocrystalline silicon wafer including a first surface and a second surface that are opposite to each other; forming a bubble layer between the first surface and the second surface of the monocrystalline silicon wafer, the bubble layer dividing the monocrystalline silicon wafer into two portions arranged side by side in a direction perpendicular to the second surface, and a portion of the monocrystalline silicon wafer that is located between the bubble layer and the second surface being a monocrystalline silicon film having a target thickness; providing a substrate, and transferring the monocrystalline silicon film onto the substrate by breaking the monocrystalline silicon wafer at the bubble layer; and patterning the monocrystalline silicon film transferred to the substrate to form active layer(s) of the thin film transistor(s).


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