The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Apr. 28, 2022
Applicant:

Huazhong University of Science and Technology, Hubei, CN;

Inventors:

Chao Wang, Hubei, CN;

Guoyi Yu, Hubei, CN;

Yi Zhan, Hubei, CN;

Bingqiang Liu, Hubei, CN;

Xiaofeng Hu, Hubei, CN;

Zihao Wang, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/15 (2006.01); G06T 1/60 (2006.01); G06T 11/40 (2006.01); G06T 3/40 (2006.01);
U.S. Cl.
CPC ...
G06T 11/40 (2013.01); G06F 17/15 (2013.01); G06T 1/60 (2013.01); G06T 3/403 (2013.01); G06T 2200/28 (2013.01);
Abstract

The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.


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