The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Oct. 11, 2019
Applicant:

Nec Corporation, Tokyo, JP;

Inventor:

Koichi Masuda, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 8/4441 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30098 (2013.01);
Abstract

A vector load instruction generating unit of a compile device generates an instruction to load a 'first group of data units', which is used as an element A[i] in iterative calculation processing, from a memory into a first vector register in a state of being packed in units of 1-word. Each data unit is (1/2)word. The vector load instruction generating unit generates an instruction to load a second group of data units, which is used as an element [i+2] into a second vector register. A vector shift double instruction generating unit generates an instruction to cause a part of a data string, which is obtained by shifting data of the first vector Register and the second register by (1/2)word as a series of data string, to be stored in a third vector register in a state of being packed in units of 1-word.


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