The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Jan. 10, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Norris Geng, San Diego, CA (US);

Richard Senior, San Diego, CA (US);

Gurvinder Singh Chhabra, San Diego, CA (US);

Kan Wang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/084 (2016.01); G06F 12/0811 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01);
Abstract

A compressed memory system includes a memory region that includes cache lines having priority levels. The compressed memory system also includes a compressed memory region that includes compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a priority level lower than the first priority level. The first set of data bits includes a greater number of bits than the second set of data bits.


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