The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Aug. 05, 2020
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Veit Kleeberger, Munich, DE;
Rafael Zalman, Markt Schwaben, DE;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G06F 11/07 (2006.01); H03K 3/0233 (2006.01); H03K 19/1776 (2020.01); H03K 19/17756 (2020.01); H03K 19/096 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0772 (2013.01); G06F 11/076 (2013.01); G06F 11/0757 (2013.01); G06F 13/1605 (2013.01); G11C 29/38 (2013.01); H03K 3/0233 (2013.01); H03K 19/096 (2013.01); H03K 19/1776 (2013.01); H03K 19/17756 (2013.01);
Abstract
A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.