The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Jun. 13, 2022
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventor:

Carsten Hermann, Dusslingen, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 3/26 (2006.01); H03K 17/687 (2006.01); H03K 17/06 (2006.01); G01R 27/14 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
G05F 3/262 (2013.01); G01R 19/0084 (2013.01); G01R 27/14 (2013.01); H03K 17/063 (2013.01); H03K 17/687 (2013.01);
Abstract

A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.


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