The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Nov. 10, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

John W. Poulton, Chapel Hill, NC (US);

Sudhir Shrikantha Kudva, Dublin, CA (US);

John Michael Wilson, Wake Forest, NC (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01);
U.S. Cl.
CPC ...
G05F 1/461 (2013.01); G05F 1/468 (2013.01);
Abstract

Systems and methods are disclosed related to low-power dynamic offset calibration of an error amplifier. An analog linear voltage regulator circuit tracks changes between a reference voltage and a regulated voltage to keep the regulated voltage as close as possible to the reference voltage. The analog linear voltage regulator includes an error amplifier that measures the error between the reference and regulated voltages and feedback circuitry. The error amplifier and feedback circuitry should be calibrated to correct for any offset within the circuits. The described offset calibration technique not only compensates for the offset in the error amplifier but also cancels any mismatch in the feedback network. During operation, conditions such as temperature and supply voltage may vary causing the offset to change. The technique is low power and dynamically cancels the offset even when the linear regulator is operating to supply the desired voltage.


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