The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

May. 19, 2021
Applicant:

Meta Platforms Technologies, Llc, Menlo Park, CA (US);

Inventors:

Andrew Samuel Berkovich, Bellevue, WA (US);

Shlomo Alkalay, Redmond, WA (US);

Hans Reyserhove, Seattle, WA (US);

Assignee:

META PLATFORMS TECHNOLOGIES, LLC, Menlo Park, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/3745 (2011.01); H04N 5/378 (2011.01); H04N 5/369 (2011.01); H04N 25/771 (2023.01); H04N 25/50 (2023.01); H04N 25/75 (2023.01); H04N 25/709 (2023.01);
U.S. Cl.
CPC ...
H04N 25/771 (2023.01); H04N 25/50 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01);
Abstract

In some examples, an apparatus comprises an array of pixel cells, and processing circuits associated with blocks of pixel cells of the array of pixel cells and associated with first hierarchical power domains. The apparatus further includes banks of memory devices, each bank of memory devices being associated with a block of pixel cells, to store the quantization results of the associated block of pixel cells, the banks of memory devices further being associated with second hierarchical power domains. The apparatus further includes a processing circuits power state control circuit configured to control a power state of the processing circuits based on programming data targeted at each block of pixel cells and global processing circuits power state control signals, and a memory power state control circuit configured to control a power state of the banks of memory devices based on the programming data and global memory power state control signals.


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