The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Aug. 13, 2020
Applicant:

Marvell Asia Pte, Ltd, Singapore, SG;

Inventors:

Guy Townsend Hutchison, San Jose, CA (US);

Sachin Ramesh Gandhi, San Jose, CA (US);

Tsahi Daniel, Palo Alto, CA (US);

Gerald Schmidt, San Jose, CA (US);

Albert Fishman, Sunnyvale, CA (US);

Martin Leslie White, Sunnyvale, CA (US);

Zubin Shah, Santa Clara, CA (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 49/109 (2022.01); G06F 3/06 (2006.01); H04L 45/64 (2022.01); H04L 45/745 (2022.01); H04L 49/1546 (2022.01); H04L 69/22 (2022.01); H04L 49/00 (2022.01); G06F 16/00 (2019.01); H04L 45/74 (2022.01); G06F 40/205 (2020.01); H04L 67/63 (2022.01);
U.S. Cl.
CPC ...
H04L 49/109 (2013.01); G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 16/00 (2019.01); G06F 40/205 (2020.01); H04L 45/64 (2013.01); H04L 45/74 (2013.01); H04L 45/745 (2013.01); H04L 49/1546 (2013.01); H04L 49/3018 (2013.01); H04L 67/63 (2022.05); H04L 69/22 (2013.01);
Abstract

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.


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